Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices

Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices
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Book Synopsis Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices by : Xiaochen Zhang

Download or read book Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices written by Xiaochen Zhang and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Characterization on SiON MOSFET devices are performed including I-V (Current-Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit a higher interface trap density (9.7E10 cm-2eV-1) than PMOS (5.8E10 cm-2eV-1). The mean capture cross sections are comparable in these devices: 3.3E-17 cm2 and 9.1E-17 cm2, receptively, for CMOS devices. Different mobility extraction methods are presented and the results indicate strong surface roughness scattering in these devices. The effects of channel carbon ion implantation (Cii) on advanced high-K metal gate low-power CMOS devices have been studies. Cii improves the device performance, especially for NMOS. The improvement comes mainly from an improvement in electron mobility, where Coulomb scattering is reduced due to retarded boron diffusion with carbon.


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