Download or read book Fabrication and Characterization of TMD FET Architectures for Increased Functionality written by Michael Allen Rodder and published by . This book was released on 2020 with total page 260 pages. Available in PDF, EPUB and Kindle. Book excerpt: The discovery of ultra-thin, van der Waals bound semi-metal (graphene), transition metal dichalcogenide (TMD) semiconductors, and insulator (h-BN), obtained via mechanical exfoliation and stacked cleanly onto one another via dry-transfers, leads naturally to the study of field effect transistors (FETs) made from these 2D materials. In this dissertation, we fabricate various conventional and newly designed field-effect transistor (FET) architectures comprised of 2D materials (for logic, memory, or synaptic applications) and report on electrical characteristics. The 2D materials used in fabrication of our FET architectures include materials for the channel region (MoS2 or WSe2), gate dielectric (h-BN), or the gate (graphene). We begin studying the FET properties of a simple 2D FET architecture (demonstrated with a MoS2 channel) which could augment Si, namely a 2D FET structure utilizing contact gating to reduce parasitic source-drain series resistance (RSD). We show that if mobility and threshold voltage (VT) are well-extracted, then this contact-gated 2D FET structure can still be easily modeled with basic FET equations, such that e.g. a conventional circuit design algorithm could implement the contact-gated 2D FET as easily as a conventional Si FET. Since contact gating is a basic feature of our 2D FET architectures, we next fabricate and characterize two novel contact-gated 2D FET architectures, with the goal being to reduce RSD, while maintaining as thin-as-possible channel layer for electrostatics and/or small subthreshold slope, for improved overall performance. The first FET architecture (single-gated; demonstrated with a WSe2 channel) improves hole injection into a single layer WSe2 channel by use of multilayer WSe2 (with smaller bandgap compared to single layer WSe2) only underneath the source (hole injecting) metal contact. The smaller bandgap multilayer WSe2 results in a smaller Schottky barrier at the metal-WSe2 interface, reducing contact resistance (RC) and thus reducing overall RSD. The second FET architecture (double-gated; demonstrated with MoS2) reduces RSD by using a MoS2 channel layer both above and below the source/drain metal contacts so that both the top and bottom gate electrostatically dope the contact regions. This reduces RSD by ~factor of 2x, and further improves the gating symmetry in MoS2 DGFETs, thus allowing for circuit design flexibility. We then move on to the fabrication of a significantly different FET architecture (i.e. not focused on a contact-gated FET architecture) that could further augment Si technology. In particular, we fabricate and characterize a device, a double-gate MoS2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG), in multiple operating conditions to demonstrate logic, memory, and synaptic applications, beyond that which could be demonstrated in a single Si-FET architecture. In our work, we noted that some of our fabricated devices exhibited a particular gate-bias-dependent kinking in I-V characteristics, which required explanation. The final chapter of this thesis thus formulates a phenomenological model, accounting for interface states at metal-semiconductor contacts, to explain the I-V kinking. The model highlights that 1) metal-semiconductor interface states need to be accounted for when modeling MoS2 FETs, and 2) the importance of forming metal-semiconductor interfaces with low interface state density to avoid I-V kinks which are detrimental for analog applications